In the last post, we gave a general overview of the semiconductor industry’s components. The “Chip intellectual Property (IP) Cores” paradigm from the earlier article will be further explained today.
Just a few words of introduction
- Top producers: ARM, Intel
- Don’t create wafers and market them.
- Give chip design businesses entire functional units, circuit design architecture, and consulting services.
- It only sells “design drawings,” often known as Silicon Intellectual Property, as there is no tangible product (SIP).
- No substantial tangible assets. Although the business is tiny in scope and has modest financial needs, its technological requirements are extremely high.
- Not be subject to the market risk associated with product sales.
- Total monopoly on the market. The X86 architecture from Intel and the ARM architecture play two significant roles in the present worldwide CPU architecture.
- While the latter virtually controls all mobile communication chips and smartphones with a market share of 95%, the former is mostly used on PCs and servers.
High-level and Low-level language for controlling computers
The majority of programming languages used today are high-level ones. High-level programming languages include C/C++ and other popular ones. High-level languages are based on English, the common language spoken by people, and they use terms that are widely understood and have a high reading level.
Computers can’t understand high-level languages, thus we must use a compiler (Complier) to turn the high-level language into a low-level language that can speak with the hardware directly.
A computer can only communicate in binary “Machine Language,” which is made up of 0s and 1s, such as 00101001010101100111. Don’t declare you’ll write till you’re crazy and it’ll be hard to even understand anything.
To make machine language easier for humans to grasp, “Assembly Language” was later created by substituting shorter strings for the 0 and 1 in machine language.
The programs written in assembly language still need to be converted into machine code by a “assembler” because the CPU only understands machine language (Assembler). A combined language’s lines directly translate to anything that resembles machine code, but it is not a high-level language.
In order for the machine to interpret the high-level language (C/C++), it must first be translated into an assembly language (Assembly Language) using a compiler (Complier), and then into machine code (Machine Code) using an assembler (Assembler). understand.
High-level languages are intended for human vision, whereas low-level languages are intended for machine. In other words, high-level and low-level language functions are distinct and cannot be directly compared.
Instruction Set Architecture: The Basics of Computer Construction
The simplest actions that a processor (CPU) can take are the “instructions” of low-level languages. An instruction set is the “whole set of all instructions” that a processor is capable of executing.
There will be details about the operation or access of data on a particular device in the low-level language commands. To understand the low-level language, engineers need hardware training. Now, building an APP or a website typically involves high-level language, so memory comprehension is not necessary. Operating hardware or the body is possible.
However, in order to construct a computer, “Instruction Collection Architecture,” a set of hardware laws relating to the instruction set, must also be created.
Let’s now tell a story on how to construct a CPU. A hardware engineer named Jason and a software developer named Allen got together one day to discuss the CPU.
“Hey, let’s develop a CPU together,” said Allen. “Let’s test our ability to work together.”
“Okay!” said Jason. ” No problem. I am in charge of developing the hardware components of the CPU, and you are in charge of writing the instructions that can be executed on the CPU. We’ll handle it independently. In a year, we will reassemble here and on the other side. integrate all at once!”
“Wait, let’s do it individually? Who knows whether it will blow up when we put it together a year from now,” Software developer Allen said. How can I be sure that the code I developed will work on the CPU you created?”
Hardware engineer Jason: “That’s fine, let’s hammer out the rules together and then build the software and hardware separately so that they can be seamlessly combined when we meet a year from now.”
The “Instruction Set Architecture” (ISA) is a rule that applies to both software and hardware.
From upstream design to downstream production, the entire IC industrial chain can be said to be based on a set of instructions that are tailored to the “software instructions” and “hardware parts to which it is attached.”
As a result, the instruction set serves as the blueprint for creating a computer. We can begin developing the computer once we have chosen the instruction set. Computers constructed using the same instruction set architecture must be able to execute every instruction in the instruction set, albeit computers built to the same specification can have various implementations.
As a result, you’ll observe that the ARM instruction set is supported by a wide range of processors (including Qualcomm, MediaTek, Spreadtrum, etc.), all of which can execute all ARM architecture instructions. The difference lies in the chips made by various manufacturers, and other competing functions like communication, photography, and other things will be added.
The cornerstone of a computer is its instruction set architecture, which also determines the kind of operating system and the level of program support. Each architecture of an instruction set has its own ecosystem. x86, ARM, MIPS, and other well-known architectures are just a few of the current instruction set architectures.
While x86, which is currently dominated by Intel, is the common architecture of personal computers, ARM, on the other hand, has a market share of up to 90% in mobile devices. Sony and Nintendo gaming consoles employ MIPS.
CISC v.s. RISC
Depending on the purpose for which the CPU was designed, the instruction set can be separated into “complex instruction sets” (CISC) and “reduced instruction sets” (RISC). Before the 1980s, the instruction set grew increasingly sophisticated, and the hardware architecture of the computer grew increasingly complicated to accommodate these instruction sets. However, just 20% of the complex instruction set’s commands are used the majority of the time, and the other 80% are only lightly used.
The idea of RISC was first put forth by the University of California, Berkeley, in 1979. With a focus on CPU execution speed, the reduced instruction set (RISC) only offers basic instructions, and the remaining sophisticated instructions are put together from basic instructions. Of course, CISC is still in existence. Both CISC and RISC have advantages and limitations, and are chosen based on the requirements for producing hardware.
A better programming environment, CISC enables objectives to be achieved with less code. It not only makes it simpler for engineers to create programs, but when the memory capacity of early computers was constrained, it can accomplish complex processes with fewer instructions.
RISC CPU specifications are substantially more straightforward. Compiling high-level languages into RISC instructions is a fairly effective way to do this (Compile). It is inexpensive to mass-produce, simple, and advances quickly. Low power consumption and power consumption are the main concerns. Low.
So, what is IP cores?
An application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA) is made up of functional blocks of logic or data called intellectual property cores (IP cores).
An IP core is a reusable logical or integrated circuit (IC) layout design unit that is frequently utilized in semiconductors. It is the intellectual property of one party, and others may obtain licenses to utilize it in their own semiconductors and ICs.
More and more system functionalities are being included into single chips in contemporary IC designs. System-on-a-chip (SOC) design is the term used to describe this kind of design. The majority of SOC chips feature a standardized microprocessor and defined functionality, allowing for licensing-based design reuse across several ICs from various suppliers. Pre-designed IP cores are important in these systems.
An IP core is typically a stand-alone component of a larger apparatus or system, such as a processor or other intricate IC. It consists of electronic circuitry that the original designer has granted other businesses a license to utilize. Before granting licenses to third parties, the designer would test the IP core.
The majority of IP cores are created using hardware description languages (HDLs), such as SystemVerilog, Verilog, or VHSIC HDL. An HDL is comparable to a piece of computer software. An IP core can also be created using a high-level specification language like C.
advantages of IP cores
Design reuse is supported by IP cores. They help electronic engineers and designers implement the unique logic and ICs’ components more quickly than they otherwise could. They support the electrical design automation sector because they allow for recurrent reuse of previously created components.
IP cores fall into three main kinds.
Hard IP core
The design of an IP is physically represented by a hard IP core. The hard IP core is often provided by the IP owner in the form of a layout design linked to a process technology. A different supplier or design studio may purchase a license to use the design for its own chip’s final configuration.
Contrary to the other two types of cores, a hard core is neither transportable nor flexible. The position and interface connectivity with other modules, clocks, and resets must be configured by the core designer. It cannot be changed for other process technologies or ported to other FPGAs because it has a fixed placement within the FPGA.
The hard IP core has the benefit of requiring less code maintenance. Due to its inclusion in the FPGA, it also reduces timing errors, promotes functionality and high performance, and offers a cheap alternative to expensive IP cores.
The hard IP core’s lack of mobility and inherent limitations are its two main drawbacks. Because of this, plug-and-play applications are where it excels. Hard IP cores are also suited for applications demanding certain signal timing or physical architectures when they are offered as mixed-signal and analog designs.
As an illustration, Mediatec worked with ARM and used their hard IP core.
Firm IP core
It is possible to configure and alter a firm IP core or semihard IP core for various uses. It offers more flexibility to position the module in the FPGA and connect it to other modules than a hard core does. Furthermore, it reduces the requirement for user-programmable setups. The firm component can be relocated around the FPGA to meet performance and timing requirements once it has been instantiated at the top level.
A firm IP core’s performance and functionality are quantifiable. Additionally, it has a slight advantage over a hard IP core due to its flexibility to support modifications. The vendor would additionally thoroughly test the core and reveal any flaws or restrictions in its documentation.
There are certain disadvantages to a strong core. Comparatively speaking, it offers less portability than a soft IP core. The source code cannot be altered, and reused copies may result in timing or performance problems.
The most adaptable sort of IP core is a soft core since it may be modified to map to any process technology and reused for a variety of applications. A list of the logic gates and connected interconnections that make up the integrated circuit (IC) may be present as an editable netlist. The code for Register Transfer Language is also an option.
Soft IP core
The licensee receives the source code along with the license when using a soft IP core. As a result, it may easily integrate the IP with its modules and alter it to fit its application. The core can be utilized by numerous FPGA kinds.
The price of a soft IP core is one of its key disadvantages. The soft core typically costs more than a hard or firm core because the provider offers the editable source code. The buyer or licensee might also need to purchase individual IP core licenses. Additionally, it might need to put in more work tailoring its applications. The performance of the application may also fluctuate and fall short of its needs.
Apple, Qualcomm, and Samsung, for instance, purchase instruction sets from ARM and then create their own circuits.
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